The present invention relates generally to integrated circuits and, more particularly, to methods for synthesizing an integrated circuit design.
Logic synthesis is a process by which an abstract form of desired circuit behavior (typically register transfer level (RTL)) is turned into a design implementation in terms of logic gates. Typical practical implementations of a logic function utilize a multilevel network of logic elements. Starting from an RTL description of a design, a synthesis tool constructs a corresponding multilevel Boolean network. Next, this network is optimized using several technology-independent techniques before technology-dependent optimizations are performed.
Finally, technology-dependent optimization transforms the technology-independent circuit into a network of gates in a given technology. Mapping is constrained by factors such as the available gates (logic functions) in the technology library, the drive sizes for each gate, and the delay, power, and area characteristics of each gate. The result of this synthesis is generally a netlist, which describes the connectivity of an electronic design.
After synthesis, the resulting netlist is used for placement and routing of the gates and other components, as well as used for additional simulations such as timing. Because the synthesis and optimization are highly numerical processes, the results generated by these processes may be very path dependent. Because of the numerical aspects of the path dependency, a side effect of synthesis tools is that generated netlists may be very different based on small changes in inputs, causing extensive efforts and repetitive work for placement, routing and timing of any updated designs.
In an ASIC chip development process, for example, once the logic synthesis and initial place and route stage have taken place, any engineering change due to RTL modification is a very complicated and time consuming task, potentially adding delay to the development process. The development process is taxed due to last minute RTL changes, as a complete new netlist is generated every time such a change occurs, forcing a time consuming manual processes to find minimal changes in the new netlist (when the new RTL has induce some additional change) as compared to the previous design.
What is needed therefore is a process that minimizes the impact of design changes late in the product development process.